SOTERIA: Exploiting Process Variation to Enhance Hardware Security Using Photonic NoC Architectures
Available for Licensing
US Utility Patent Pending
At A Glance
- A two-part solution for improving hardware security for Photonic Network-on-Chip (PNoC) architectures, which includes encryption and authentication signatures, as well as a reservation waveguide and switching methodology.
- The main problem this technology solves is significantly reducing the chance of a hardware trojan snooping on private data.
- The first market is the semiconductor industry. The second market is the high-performance technology industry (i.e. neural networks, internet of things, supercomputers etc)
Complexity of hardware in modern chip-multiprocessors has increased to cope with the growing performance demands of modern Big Data and cloud computing applications. Chip-multiprocessor devices may use photonic networks-on-chip (PNoCs) to form packet-switched network fabrics over the processing cores to transfer data either between on-chip components for inter-core communication or between devices for inter-chip communication. Recent developments in silicon photonics have enabled the integration of photonic components to interconnect with CMOS circuits on a chip. PNoCs provide several prolific advantages over traditional metallic counterparts, including the ability to communicate at near light speed, larger bandwidth density and lower dynamic power dissipation.
The invention provides hardware-circuit-level encryption for inter-core communication of PNoC devices to protect data from snooping attacks. This includes encryption using authentication signatures that are based on process variations that inherently occur during the fabrication of the photonic communication device. The hardware level encryption can facilitate high bandwidth on-chip data transfers while preventing hardware-based trojans embedded in components of the PNoC device or preventing external snooping devices from snooping data. Additionally, there is an architecture-level reservation operation that decouples the photonic waveguide and a reservation waveguide to secure the photonic communication device from internal or external snooping or manipulation.
- Currently, no prior work has analyzed security risks in photonic devices and links, or considered the impact of these risks on PNoCs
- Technology provides circuit-level security enhancement as well as architecture-level security enhancement
Sai Vineel Reddy Chittamuru, Ishan G Thakkar, Varun Bhat, Sudeep Pasricha, SOTERIA: Exploiting Process Variations to Enhance Hardware Security with Photonic NoC Architectures” Nov 21, 2017
Last updated on October 7, 2019.