Switched Memory Architectures
Implemented directly in the silicon architecture, this integrated circuit technology benefits advanced (including optical) computing.
Available for Licensing
US Utility Patent: US 7412586
At a Glance
A Switched Memory Architecture (SMA) is a domain specific architecture designed for direct hardware implementation of a class of compute-intensive programs called Affine Control Loops (ACLs). An SMA is essentially, a multi-dimensional grid of processors or processing elements (PEs), each one consisting of (i) a functional unit that implements a data path to execute the operations in the loop body, (ii) a control unit and (iii) a set of memory banks to store the results of the computations. The PEs are interconnected through a special interconnection network called the GRAIL (Generic Reconfigurable Affine Interconnection Lattice).
Tech Mgr: TBD
Reference No.: 03-039
With the widespread use of high performance embedded devices in “information appliances” such as cell phones, PDAs, and other hand-held devices, the electronic design industry is faced with the challenge of reducing the cost and design time of high-performance embedded systems.
Researchers at Colorado Statue University have developed switch memory architectures (SMAs), is a class of parallel architectures intended for a direct silicon implementation in either electronic or optical systems. SMAs may be systematically derived and are suitable for a wide range of targets. Derivation and application-specific configuration of SMAs use a well-developed mathematical formalism called the polyhedral model, which permits the expression of compute intensive algorithmic kernels and systematic derivation of SMA tailored specific kernel.
SMAs are related to, but more powerful than, an earlier technology called systolic arrays. Systolic arrays are an n-dimensional, locally connected grid of simple processing elements (PEs) wherein each PE is pre-configured for a specific task and thus has no instruction overhead. Precise data-transfer and control between the PEs result in the parallel solution of the application. In contrast, SMAs are a grid of PEs connected through the ISWITCH that allows long connections that can be rapidly, easily and dynamically reconfigured. The reconfiguration, however, is restricted in scope and thus has a low cost. Nevertheless, they are necessary and sufficient for an efficient (optimal under certain constraints) regular implementation of the targeted applications.
In contrast to systolic arrays, in which the grid is usually one or two dimensional, SMAs reasonably have a minimum of three dimensions and are as a result particularly relevant for optical or 3D VLSI. The higher dimensionality is possible because SMAs relax the “locality-constraint” on the PEs of systolic architectures.
In summary, SMAs are a new architectural model intended for direct silicon implementation in either electronic or optical systems. On-chip memory may be used to store and transfer intermediate values, and reconfiguration may be used for run-time switching of the memory-processor interconnect. A device of the present invention may be suitable for a wide range of target technologies ranging from ASIC and FPGAs to more general reconfigurable computing platforms.
Features & Benefits
- Switch memory architectures (SMAs) are a new model of parallel architectures intended for direct silicon implementation in either electronic or optical systems, including 3D VLSI.
- SMAs relax the locality constraint inherent to the systolic model, which they generalize and improve. They can be automatically derived from high-level program specifications.
- SMAs are suitable for a wide range of target technologies, from ASIC and FPGAs to more general reconfigurable computing platforms.
Rajopadhye, Sanjay, et al. “A Domain Specific Interconnect for Reconfigurable Computing.” ACM SIGPLAN Notices, ACM, dl.acm.org/citation.cfm?id=1379023.1375669&coll=ACM&dl=ACM.